Trade-offs for High Yield in 90 nm Subthreshold Floating-gate Circuits by Monte Carlo Simulations

The work described in this paper is performed to estimate the influence of statistical process variations and transistor mismatch that occurs in fabrication and affect floating-gate digital circuits. These effects will affect and reduce “yield” (percentage of fully functional circuits). Monte Carlo simulations have been performed in a 90 nm to estimate the yield for manufactured floating-gate circuits running with subthreshold power supply. The power supply, floating-gate charge voltage (VFGP and VFGN) and transistor sizes have been varied during the simulations and the yield has been observed. The simulation results shows that by doubling the minimum size transistors (length and width) the yield can be much better than for minimum size version. A yield of 100% can though not be expected if the power supply is scaled down below 250 mV.